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Burn-in & Test Strategies WorkshopTM |
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ADVANCE
PROGRAM |
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Technical
Program
Once again,
the BiTS Workshop offers a robust and
riveting program featuring 30+ papers
presented during 7 podium and two poster
sessions covering a host of test and
burn-in related topics from a worldwide
representation of authors. |
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Tutorial
Get set
for another nostalgia trip. He was such
a big hit in 2006 with over 70
attendees, that we’ve brought Dr. Roland
Timsit back for a refreshed course on
the “Fundamental Properties of
Electrical Contacts”. The seminar
addresses how contact force and the
mechanical properties of contact
materials affect both contact resistance
and the electrical/mechanical integrity
of an electrical contact device. Sign up
early as this one will fill up fast.
TechTalk
Building
on his 2006 “Geometric Dimensioning and
Tolerancing” primer tutorial, which
regularly tops the BiTS charts as most
frequently downloaded archived
presentation, Thomas Allsup returns to
further enlighten BiTS Workshop
attendees with an exciting look at GD&T
fundamentals, an explanation of changes
in the new ASME Y14.5-2009 standard, and
an in-depth examination of actual
semiconductor GD&T drawing examples.
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Distinguished and
Keynote Speakers
Get a
glimpse of the future of burn-in and
test strategies from renowned Keynote
and Distinguished speakers. These
industry visionaries will give attendees
something to think about in advance of
the Technical Program.
EXPO 2012
Everything
you need to know about what’s NOW and
NEXT in packaged IC burn-in and test
products and services, you’ll find at
this year’s BiTS EXPO. The BiTS EXPO
features a collection of global
companies showcasing their latest
innovations. Browse, explore and chat
with knowledgeable reps. Click
here for an up-to-date list of
exhibitors.
Schedule
At-a-Glance |
Marketplace Reports
This one
is sure to be standing room only, so
don’t be late! Jon Diller of
Interconnect Devices, Inc., shares his
insights on the ‘geography’ of sockets,
while Jim Brandes of Multitest shines a
light on what socket specifications
really mean. And once again, BiTS
General Chair, Fred Taber, looks to spur
discussion with a fresh analysis of the
burn-in and test socket market in his
annual Socket Marketplace Report.
Networking
Let’s face
it, this is the REAL reason for
attending BiTS 2012; ask anyone who’s
been to a previous BiTS Workshop. Why?
Numerous meals, breaks, and receptions
give attendees the opportunity to
compare notes with colleagues from
around the world while soaking up the
Arizona sunshine.
Laissez les bons temps rouler at the
BiTS Bayou Bash featuring Cajun cuisine
and New Orleans–style Jazz. You’ll think
you’ve died and gone to Bourbon Street. |
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Read below for complete program details
Schedule is subject to change at any time |
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Premier
Sponsor: |
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Distinguished Sponsors: |
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Publication Sponsor:
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TUTORIAL
DAY
Sunday, March 4, 2012 |
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TechTalk |
GD&T for Burn-In and Test Professionals |
noon - 3:00 |
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Thomas Allsup
President
Anida Technologies |
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Geometric Dimensioning and Tolerances (GD&T) is the
common language used to describe the allowable variances of manufactured feature
sizes, shapes, and locations beyond that which can be controlled by regular
rectilinear and angular dimensions and tolerances.
Semiconductor component and socket manufacturer drawings both
use GD&T to insure their respective components fit and function mechanically
together.
The “How to Spell GD&T” tutorial previously presented at BiTS
provided a detailed primer of how to read GD&T symbols on drawings and provides
an introduction to this tutorial.
This new tutorial is presented in three sections: Section one
provides a highly abbreviated “How to Spell GD&T” review of the fundamentals of
GD&T, Section two explains the first changes to the ASME Y14.5 standard in
fifteen years, particularly where those changes impact semiconductor
professionals, and Section three contains a series of public domain
semiconductor component drawings that will be carefully dissected to explain how
GD&T was used correctly and incorrectly. |
Who Should Attend:
Mr. Allsup will introduce and explain the symbolic based language
of GD&T and provide a handy tool – a periodic table of GD&T symbols. Attendees
who are new to GD&T will receive a solid foundation of the nomenclature and
their correct usage while experienced designers will have a chance to discuss
many practical applications as the topic relates to socket tolerancing. |
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Limited Complimentary Attendance – see Registration page for
details |
| Thomas Allsup is the Managing
Partner of Anida Technologies, a Dallas based design contract services
company and has twenty four years of experience in various engineering
roles. Thomas earned a BSME from Oklahoma State University and an MSME
from the University of Texas at Arlington. He has experience in the
design of fixtures for back-end semiconductor processes, including the
design and manufacture of custom semiconductor burn-in and test sockets,
and provides training in many technical subjects including CAD, GD&T,
and DFMA. |
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Tutorial |
Fundamental Properties of Electrical Contacts |
3:30 - 6:30 |
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Dr. Roland S. Timsit
President
Timron Scientific Consulting, Inc. |
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interface between two solids is generated by contact between
protruding surface asperities on each of the contacting bodies, so
that mechanical contact is actually established at a discrete number
of contact spots. Because these spots are tiny, the area of true
contact is very small and electrical current passing through the
interface is highly constricted at these spots. Constriction of the
current gives rise to contact resistance.
The seminar addresses how contact force and the
mechanical properties of contact materials affect both contact
resistance and the electrical/mechanical integrity of an electrical
contact device. Selected contact properties of materials and
electroplates such as gold, tin and silver are reviewed. The
deleterious effects of contaminant and corrosion surface films, and
other mechanisms such as mechanical wear and fretting corrosion,
that conspire to eliminate electrical contact spots, are described.
The nefarious effects of these mechanisms can often act rapidly,
with ensuing catastrophic failure, in devices where the contact
force is small such as in MEMS. The effect of signal frequency on
contact resistance will also be addressed. |
Who should attend:
Dr. Timsit will build on his 2006 tutorial covering the
fundamentals of interfacial contacts. The tutorial is geared for
attendees with a basic knowledge of electrical contacts. Dr. Timsit
usually teaches this material over a multi-day course, so this BiTS
tutorial will be packed with information for professionals seeking a
broad, yet comprehensive understanding of electrical contacts. |
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Additional registration
fees apply - see Registration page for details
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| Dr. Timsit spent 20 years in R&D in
the aluminum industry where he focused on power connector design,
aluminum surface modification, connector cable alloys, lubrication,
brazing and metalworking.
In 1994, he joined AMP Inc. (now TE
Connectivity/Tyco Electronics) and led technology development for the
AMP Power Technology Division as Chief Technologist.
Dr. Timsit is a recipient of the IEEE Ragnar Holm
Scientific Award for innovative research in electrical contacts. He is
also a recipient of four international awards relating to electrical
contacts and metal joining. He has authored of over 130 papers, including
Chapter I of the IEEE Book Publication "Electric Contacts: Theory and
Applications", and holds 15 patents.
Over the last thirteen years, Dr. Timsit has served as
President of Timron Scientific Consulting Inc., Toronto, Canada, a
provider of technology support to electronic/electrical connector
manufacturers and users in the Americas, Europe and Asia.. |
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Opening Night Welcome
Reception |
Sponsored by: |
6:30 - 7:30 |
| Dinner |
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7:30 - 8:30 |
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Marketplace Reports |
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8:30 - 9:30 |
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This year’s Marketplace segment of the BiTS program, offers 2 new and
unique topics and reprises last year’s report on the business side of
sockets with fresh data. |
| "The ‘Geography’
of Sockets" |
Jon Diller
IDI, Smith Group |
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| "Specsmanship" |
James Brandes
Multitest |
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"Socket
Marketplace Report" |
Fred Taber
BiTS Workshop |
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BiTS
2012 TECHNICAL PROGRAM - SESSIONS
MORE THAN 30 PAPERS AND POSTERS
The Latest Information on Important
Topics in Burn-in & Test of Packaged ICs will be Presented
at 7 Podium Sessions and Two Poster Sessions |
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PROCESS
DAY
Monday, March 5, 2012 |
| Opening
Remarks |
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8:30 - 9:00 |
| Welcoming remarks from the General
Chair, Fred Taber |
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BiTS 2012 Keynote
Address
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Packaging the Next Driver |
9:00 - 10:00 |
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Jim Feldhan
President
Semico Research |
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Mr. Feldhan will provide a brief economic overview
along with Semico’s Semiconductor Forecast. As ICs become more complicated and
push the technology roadmap, system performance and chip to chip interaction is
becoming a limiting factor. The result, test and packaging is coming to the
forefront. 2.5D and 3D package offer great advantages, yet there are still
technical issue to overcome. Mr. Feldhan will present the Semico roadmap to 3D
packaging, the end products that adopt 3D and how that adoption will evolve over
time. |
| Jim Feldhan founded Semico Research
in 1994. A 20-year veteran of the semiconductor industry, he brings his
management, forecasting and modeling expertise to Semico, along with a
reputation for quality research. Jim designed and developed the research
methodologies and report structures, which are the basis for Semico’s
Custom Research and Portfolio Services. He also develops Semico’s
overall economic outlook as well as performing various semiconductor
consulting and forecasting. With a focus on quality, Semico Research has
grown to be the largest semiconductor-focused consulting and research
firm.
Jim was formerly the Executive Vice-President and
General Manager at In-Stat. As a member of the start-up team there, he
was responsible for the design, methodologies, and implementation of
research that was the basis for the Semiconductor Services.
Mr. Feldhan also held various management, marketing
and manufacturing positions at GTE Microcircuits and Greyhound/Dial
Corporation. He received a BS in Business with a minor in Chemistry from
the University of Arizona and a MS in Marketing focusing on quantitative
statistics and market research from the University of Arizona. |
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Session 1 |
The
Tricks are in the Tooling |
10:30 - 12:30 |
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What do today's burn-in process, power delivery efficiency, DUT temperature
control, pin characterization and socket qualification all have in common?
They're all being challenged by smaller geometries, increased power with
localized densities and thermal conditions, all compounded with a need to
produce solutions in less time at lower cost. Speakers in this session have
come up with some innovative solutions such as a novel approach to
addressing burn-in challenges with a thermal interface material, managing
electrical, mechanical and thermal challenges for high current
implementation in a temperature-humidity system, managing DUT temperature
using LN2 injection and the development of a programmable tool to
characterize socket pins. |
| "Burn-in Process
Thermal Challenges With High End Applications" |
Oswaldo Chacon
IBM Canada |
Alexandre Leblanc
IBM Canada |
Martin Laliberté
IBM Canada |
Benoît Foisy
IBM Canada |
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"High Current
Implementation in a Temperature-Humidity System" |
John Pioroda
Incal Technology, Inc. |
Naveed Syed
Incal Technology, Inc. |
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"DUT Temperature
Control Using LN2 Injection" |
Joseph Mayfield
Texas Instruments |
Nolan Riley
Texas Instruments |
Chad Turner
Texas Instruments |
"Sophisticated
Tool for Pin Characterization and Socket Qualification" |
Praveen
Kumar Ramamoorthy
Intel Corporation (Malaysia) |
K. W. Low
Intel Corporation (Malaysia) |
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BiTS 2012 Distinguished Speakers |
Package
Level Test Challenges – Delivering More Than a Technology |
1:30 - 2:30 |
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John Morrissey
ATCED Test
Tooling Manager
Intel Corporation |
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Mark Hopman
STTD Wafer Test &
Tooling Manager
Intel Corporation |
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Moore’s law continues to set the
pace for the Microprocessor industry driving transistor density, performance
and rich capabilities even as ASPs drift down. Test capital has stretched to
keep up through improved parallelism, advanced architectures and in-field
configurability while test tooling quality, lead time and cost are starting
to fall behind. New technology needs will continue to challenge test tooling
but are more evolutionary in nature while the business drivers have grown to
be critical.
We are seeing an inflection in the test tooling industry’s future where
traditional test strategies will evolve. Quality, lead time and cost will
dominate tooling choices and be the future engine to enable quicker time to
market, a more nimble business and improved cost competitiveness. Test
tooling has moved from a commodity to an integral business enabler. Tight
collaboration between supplier and customer will be paramount. We will share
key tooling business trends, challenges and what can be done to enable
future opportunity and growth in this industry.
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Mr. Hopman leads Intel’s Sort
Module and Package Test Tooling technology development team. His 25 year
career at Intel has focused on Product Engineering, Sort Factory
Management, and test module and tooling development.
Mr. Morrissey manages the test tooling team within Intel’s Assembly Test
Capital Equipment Development (ATCED) organization. In his 18 years at
Intel, he has spent the majority of his time managing supplier teams and
ensuring Intel’s factory needs are met on time and within expectations.
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Poster Session 1 |
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2:30 - 3:30 |
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Sure, podium presentations are great, but sometimes it’s
nice to have a one-on-one chat with the author. And, we all wonder: how many
people are inclined to ask those provocative questions in front of the whole
audience?
With a variety of topics being addressed, poster sessions
offer the perfect opportunity for authors and attendees to interact directly
and even share ideas in an informal setting while enjoying some
refreshments. |
| "IM Material for
High Strength Test Socket" |
Jiachun
(Frank) Zhou
IDI, Smith Group |
Dexian
Liu
IDI, Smith Group |
Khaled
Elmadbouly
IDI, Smith Group |
Brad Henry
IDI, Smith Group |
Kevin DeFord
IDI, Smith Group |
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| "Socket Spring
Probes - Degradation Experiments" |
Shaul Lupo
Intel Corporation |
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“Low Force SuperButton® Connector Technology” |
Amit Varma
High Connection Density, Inc. |
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“Use of Conical Inductors for Load Boards Testing” |
Gustavo Cozacov
Intel Corporation - Israel Development Center |
Maroon Maroon
Intel Corporation - Israel Development Center |
Isar
Reichman
Intel Corporation - Israel Development Center |
Tali Korin
Intel Corporation - Israel Development Center |
Shimon Manor
Intel Corporation - Israel Development Center |
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Session
2 |
Operations Matter |
3:30 - 5:30 |
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It's amazing what streamlining burn-in and test operations and processes can
do for your bottom line. This session focuses on optimized methods developed
to improve throughput, increase yields and extend the life of the equipment
itself. First, you'll hear about using test-in-tray methods to effectively
test devices under rigorous thermal regimes and power levels. The second
speaker will explain an alternative manufacturing method for rapid
prototyping of test socket. A presentation on optimized online socket
cleaning promises improved yields and reduced retest. Wrapping up the
session will be a paper on how alternative coatings can improve contact
life. |
| "High Performance
Testing of Semiconductor Devices with Test-in-Tray Formats" |
Thomas H. Di
Stefano
Centipede Systems |
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| "Using
Alternate Manufacturing Methods for Rapid Prototyping of Test
Sockets" |
James Migliaccio
RF Micro Devices |
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| "Consistent
On-Line Test Socket Cleaning for First Pass Yield Stability and
Reduced Retest" |
Jerry Broz Ph.D.
International Test Solutions, Inc. |
Bret Humphrey
International Test Solutions, Inc. |
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| "Achieving
Extreme Contact Life Through The Application of Alternative
Coatings" |
Erik Orwoll
Contact Coatings, LLC |
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DEVELOPMENT
DAY
Tuesday, March 6, 2012 |
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Session 3 |
Analyze This |
8:00 - 10:00 |
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What good is it to have optimized test devices if the characterization and
analysis processes aren't up to speed as well? This session focuses on the
whole picture. We open with methods for taking device specifications and
translating them into test contactor requirements to reduce the impact of
testing the device in the contactor. Next we'll move on to the challenges of
balancing signal integrity with power integrity through the socket and PC
board. The session wraps up with two presentations investigating parameters;
the first discusses key parameters of pulse current testing and their
significance and the second shares some crucial parameters in thermal
simulations. |
| "Understanding
Specs to Better Simulate Solder to Board Performance" |
Jeff Sherry
Johnstech International Corporation |
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| "Mitigating Test
Interconnect Issues for the Next Generation of High Speed, High
Power Devices" |
Thomas P. Warwick
R&D Circuits, Inc. |
Al Seier
R&D Circuits, Inc. |
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| "Pulse Current
Testing: Parameters and Their Significance" |
Gert Hohenwarter
GateWave Northern, Inc. |
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| "Key Parameters in
Thermal Simulations" |
David Pfaff
Plastronics Sockets & Connectors |
Mike Ramsey
Plastronics Sockets & Connectors |
Joe Ortega
Plastronics Sockets & Connectors |
Larry Furman (presenter)
Plastronics Sockets & Connectors |
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Poster Session 2 |
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10:00 - 11:00 |
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Sure, podium presentations are great, but sometimes it’s nice to have a
one-on-one chat with the author. And, we all wonder: how many people are
inclined to ask those provocative questions in front of the whole audience?
With a variety of topics being addressed, poster sessions offer the perfect
opportunity for authors and attendees to interact directly and even share
ideas in an informal setting while enjoying some refreshments. |
| "Novel
Approach for Detecting and Diagnosing Load Board Problems Before HVM
(High Volume Manufacturing) Production Run" |
Maroon
Maroon
Intel Corporation - Israel Development Center |
Gustavo
Cozacov
Intel Corporation - Israel Development Center |
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"Development of Pressure Sensitive Conductive Rubber (eM-PCR® /HAH-PCR®)" |
Josh Jin
WinWay Technology Co., Ltd. |
Hiroe Mochizuki
WinWay Technology Co., Ltd. |
Jack Liang
WinWay Technology Co., Ltd. |
Daisuke Yamada
JSR Microtech Inc. |
Kazuhiro Chishima
JSR Microtech Inc. |
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| "BGA
Spring Probe for Fine Pitch/High Current" |
Fred Megna
MJC Electronics Corp. |
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| "Tools
for the Trade - Maximizing Our Resources" |
Jay Kim
Western Specialty Technologies LLC |
Victor Pyo
OKins Electronics Co. Ltd. |
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Session 4 |
Making
Contact |
11:00 - 12:30 |
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For many socket and probe card manufacturers the pins are the secret sauce,
especially when performing burn-in and test on today's devices that have
increasingly finer pitch and smaller geometries. This session will feature
three presentations offering different contact solutions. The first speaker
presents a new technique for fine pitch applications that integrates a short
wiping stroke. Next up is a high-volume low-cost stamped spring probe in
development for burn-in sockets. The session closes with a presentation on a
simple, yet effective contact pin geometry. |
| "A
New Short-wiping-stroke (SWS) Technique for Fine Pitch Application" |
Ying Hoe Mah
JF Microtechnology Sdn. Bhd. |
Jay Williams
Transcend Technology LLC |
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| "High
Volume Low Cost Stamped Spring Probe Development" |
A.J. Park
IWIN Co. Ltd. |
Jimmy Johnson
Materion Brush Performance Alloys |
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| "Simple
and Effective Contact Pin Geometry" |
Bert Brost
Nuwix Technologies |
Marty Cavegn
Nuwix Technologies |
Don Fulcher
Nuwix Technologies |
Tom Inwood
Nuwix Technologies |
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Session 5 |
Designing for Performance |
1:30 - 3:30 |
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It just wouldn't be a BiTS Workshop without a session devoted entirely to
novel socket designs. Every year, there are new devices on the market and
ever critical factors like witness marks on smaller solder balls and minimum
contact force that need a socket designed specifically for them. The four
papers in this session address four distinctly different socket
applications. The first is a new MEMS socket for a fine pitch device. The
second presentation gives a face lift to an existing socket design: a
terraced methodology for a multilayer ceramic socket for wafer-level
packages (WLP) that makes the socket easier to manufacture at an affordable
price. The third paper reviews the heat path for a device mounted in a
socket and discusses the important variables in a thermal analysis. Lastly,
we'll examine the design of a wall-extended coaxial socket. |
| "Embedded Barrel
Contactor - Solution for Small Pitch Socket" |
Jiachun (Frank) Zhou
IDI, Smith Group |
Dave Henry
IDI, Smith Group |
Praba Prabakaran
IDI, Smith Group |
Tim Marshall
IDI, Smith Group |
Khaled Elmadbouly
IDI, Smith Group |
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| "Evaluation
and Optimization of the Thermal Performance of a Socketed Device for
an HTOL Application - Considerations in the selection of a socket
for a plastic molded, thermal enhanced package" |
Nathanaël
Loiseau
Presto Engineering |
Marco Michi
WELLS-CTI |
Dr. James
Forster
WELLS-CTI |
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"Wall-extended Coaxial Socket" |
Collins Sun
WinWay Technology Co., Ltd. |
Justin Liu
WinWay Technology Co., Ltd. |
Jack Liang
WinWay Technology Co., Ltd. |
Kuan-Chung
Lu
National Sun Yat-Sen University |
Tzyy-Sheng
Horng
National Sun Yat-Sen University |
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BiTS Bayou Bash
A Taste of New Orleans |
Reception, Cajun
cuisine, games, with a background of great jazz. |
6:30 - 9:30 |
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PERFORMANCE DAY
Wednesday, March 7, 2012 |
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Session 6 |
We’ve
Got the Power (and Signal Integrity)! |
8:00 - 10:00 |
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Power delivery and signal integrity have become increasingly important
issues in device testing, especially for today's mobile electronics that
require more of both to achieve the levels of functionality expected by
consumers. As a result, they are becoming some of the greatest challenges in
designing test interfaces. In this session, presenters report on a number of
specific developments that address these challenges. The first presentation
will address the point of diminishing returns on socket pin length from a
signal integrity perspective. Next, we'll learn about the anatomy of PCB
vias in single-ended and differential signal paths. The third speaker will
offer solutions for improving power delivery in the test interface. Finally,
innovative interconnect evaluation metrics for design optimization will be
explained. |
| "Point
of Diminishing Returns on Socket Pin Length From a Signal Integrity
Perspective" |
Sasha N.
Oster
Intel Corporation |
Selim Sermet Akbay
Intel Corporation |
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"The Anatomy of PCB Vias in Single-ended and Differential
Signal Paths" |
Zaven Tashjian
Circuit Spectrum, Inc. |
Kevin Chan
Circuit Spectrum, Inc. |
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"Improving Power Delivery in the Test Interface" |
Ryan Satrom
Multitest |
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"New Interconnect Evaluation Metrics for Design Optimization" |
Se-Jung Moon
Intel Corporation |
Richard
Mellitz
Intel Corporation |
Erkan Acar
Intel Corporation |
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Session 7 |
Living
in a Material World |
10:30 - 12:00 |
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When you think about it, advanced materials are the steroids of the device
testing world. The right material can often make the impossible possible. In
this session, we hear about the improvements three innovative materials make
to previous technologies. The first presenter introduces a new socket
material that improves the strength and insulation properties of composite
plastics, and demonstrates this in two socket designs. The second speaker
examines socket contact plating and the impact on contact resistance in a
burn-in environment. The final presenter talks about developing clad alloys
for manufacturing test and burn-in sockets that better withstand the stress
relaxation induced by high temperatures without sacrificing strength and
performance. |
| "IM Material for
High Frequency Test Socket" |
Jiachun
(Frank) Zhou
IDI, Smith Group |
Dexian
Liu
IDI, Smith Group |
Khaled
Elmadbouly
IDI, Smith Group |
Brad Henry
IDI, Smith Group |
Kevin DeFord
IDI, Smith Group |
|
"Socket Contact Plating and the Impact on Contact Resistance in
a Burn-in Environment" |
Mike Noel
Freescale Semiconductor |
Shawn Toth
Enplas Tech Solutions, Inc. |
|
"Using Clad Alloys to Make High Temperature Burn in and Test
Sockets" |
Jimmy Johnson
Materion Brush Performance Alloys |
Terry Morinari
Enplas |
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| Awards
/ Closing Remarks
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12:00 - 12:30 |
| It's been three days packed with
learning, exploring and sharing, but now it's time to pack our bags and
take what we've learned back to our jobs. But first, there are a few
closing remarks and some recognition to the people and papers that have
distinguished themselves in one way or another at BiTS 2012.
Watch the BiTS website for the posting of BiTS 2012
presentations, attendees, Exhibitor directory, photos, and for news about
BiTS 2013. |
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Page last modified
02/02/12
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BiTS WorkshopTM is a production of
BiTS Workshop LLC |
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