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BiTS 2012 Call For Presentations
2012 Expo Registration
2012 Sponsorship and Advertising  
2012 Attendee Registration Opens December 2011
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BiTS is the world's premier workshop dedicated to providing a forum for the latest information about burn-in and test tooling, and related fields. At BiTS you'll find a comprehensive technical program, exhibits of the latest products and services, and many opportunities to meet, network and explore ideas with other test and burn-in strategies professionals.

 

 

For an electronic copy of this call for papers in Adobe(R) Acrobat(R) (.pdf) format, the following file can be downloaded:

bits2012cfp.pdf  PDF

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March 4-7, 2012 Mesa Arizona

CALL FOR PRESENTATIONS

The 2012 BITS Workshop is seeking presentation  and poster proposals on a broad range of topics.

DEADLINE EXTENDED TO NOVEMBER 1, 2011

ABSTRACT SUBMISSION

Become a BiTS author! Contribute to a stimulating and comprehensive program by sharing your latest work and advancements with colleagues from around the globe.
Don’t wait. Submit a 250 to 500 word abstract of your original, previously unpublished, technical presentation by October 14, 2011 November 1, 2011 to .

Include with your emailed submission:

  • TITLE OF PRESENTATION

  • EACH AUTHOR’S name, affiliation, postal and email addresses, telephone number(s). Identify who the presenter will be.

For further information, questions or comments, please contact the BiTS Office at:  or by phone
at 845-226-7560.

Abstract reviews /selections will be completed, and authors notified, on or about NOVEMBER 15, 2011.


Some topic ideas include Techniques and Technologies that address:

ELECTRICAL & MECHANICAL CHALLENGES

  • WLCSP Test for KGD or Final Test
  • Wafer Level Packages, Thinner Packages & PoP
  • Design tools: GD&T; FEA, etc.
  • Ball deformation & package stress
  • Package alignment
  • High frequency; high data rate; high current techniques and technologies
  • Handler & change kit designs and considerations
  • Managing ESD
  • Fine Pitch Kelvin Contacting
  • Automotive semiconductor requirements
  • Thermal management and modeling
  • Contact technology: dissimilar metal interface degradation, carbon nanotube developments, non-traditional interface materials, contact reliability in test and burn-in conditions
  • Socket and contactor contact cleaning methods
PCB DESIGN AND MANUFACTURING CHALLENGES
  • For high temperature Burn-in board applications
  • High data rate test applications
  • Space Transformers
  • Ultra-fine pitch
  • Board to Board Interconnects
  • CTE, force & planarity issues

ADVANCED PACKAGING TECHNOLOGIES

  • Minimizing metals & plating of material
  • Low power and/or alternative power
  • Lead-Free
  • Reducing/recycling materials used in shipping sockets, PCBs and other products
  • Interconnect solutions for photovoltaic products
  • Cradle to cradle manufacturing

TEST PROCESS & OPERATIONAL CHALLENGES

  • Test & Burn-in floor operations
  • Socket repair and cleaning methods
  • Value Engineering: methods and techniques for reducing cost of ownership, achieving low-cost burn-in, etc.
  • Massively parallel test
  • Test strategies for shorter consumer product cycles
  • Socket & PCB checkout & qualification
  • Strip Testing
  • Test-in-Tray
  • Wafer Level Testing

Page last modified 10/13/11

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